
############################################################################
# Clock constraints                                                        #
############################################################################

set_false_path -from [get_clocks clk_fpga_0] -to [get_clocks adc_clk]
set_false_path -from [get_clocks clk_fpga_0] -to [get_clocks par_clk]

### SATA connector
set_property IOSTANDARD DIFF_HSTL_I_18 [get_ports {daisy_p_o[*]}]
set_property IOSTANDARD DIFF_HSTL_I_18 [get_ports {daisy_n_o[*]}]
set_property IOSTANDARD DIFF_HSTL_I_18 [get_ports {daisy_p_i[*]}]
set_property IOSTANDARD DIFF_HSTL_I_18 [get_ports {daisy_n_i[*]}]

set_property PULLUP true [get_ports {daisy_p_i[1]}]

set_property PACKAGE_PIN U18 [get_ports {adc_clk_i[1]}]
